Exemplary embodiments relate to a method of operating a semiconductor memory device.
A NAND flash memory device, which is nonvolatile, includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines elongated in rows, a plurality of bit lines elongated in columns, and a plurality of cell strings corresponding to the respective bit lines.
The functions of the semiconductor memory devices are gradually improved through high degree of integration and increase in the capacity while reducing the chip size.
In order to further advance high integration of semiconductor memory devices, a multi-bit cell design is studied for storing more than one data in a single memory cell. This type of the memory cell is called a multi-level cell (MLC). A memory cell capable of storing one bit is called a single level cell (SLC).
The multi-level cell utilizes a plurality of threshold voltages with an increase in the number of bits that can be stored. With high integration, a narrower gap exists between memory cells.
Accordingly, while a program operation is performed in a semiconductor memory device, the threshold voltages of memory cells can be shifted due to a coupling effect caused by the threshold voltages of neighboring memory cells.